1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device having a two-layer gate electrode transistor stacked with floating and control gate electrodes. Moreover, the present invention relates to a method of manufacturing the foregoing same device.
2. Description of the Related Art
A NAND flash EEPROM has been known as a non-volatile semiconductor memory device having a two-layer gate electrode transistor. The NAND flash EEPROM includes a shallow trench isolation (STI), a gate insulating film, a two-layer gate electrode, and a source/drain region. The shallow trench isolation (STI) functions as several element isolation regions formed in a substrate. The gate insulating film is formed on the substrate across STIs. The two-layer gate electrode is composed of a floating gate electrode, an intergate insulating film and control gate electrode, which are successively stacked on the gate insulating film. The source/drain region is positioned on both sides of the two-layer gate electrode, and formed in the substrate. The upper surface (thickness) of the STI is formed thicker than the surface of the gate insulating film, and set to approximately half of the height of the floating gate electrode. The control gate electrode on several floating gate electrodes is continued to form a word line. The floating gate electrode along the word line has a sectional structure such as a rectangular shape having a height longer than the base side. In other words, the upper surface of the floating gate electrode is set thicker (higher) than that of the STI. The gate insulating film is formed on both sidewalls of the floating gate electrode and the upper surface thereof, and on the STI.
The coupling capacitance of the two-layer gate electrode having the foregoing structure is as follows. Specifically, the capacitance of the gate insulating film below the floating gate electrode is set as Ctox, and the integrate capacitance is set as Cip. In this case, a coupling capacitance Cr is expressed using the following equation.Cr=Cip/(Cip+Ctox)
Namely, the area of the intergate insulating film existing between floating and control gate electrodes gives an influence to the coupling capacitance.
According to the structure of the foregoing two-layer gate electrode, a contact area of the floating gate electrode and the intergate insulating film is increased, thereby increasing the coupling capacitance. There exists a method of increasing the contact area. According to the method, the film thickness of the floating gate electrode is formed thicker, thereby increasing the area of the intergate insulating film.
However, the foregoing method has the following problems. Specifically, in order to form a gate electrode, materials for the floating gate electrode, intergate insulating film, control gate electrode and mask are successively stacked. The control gate electrode material is etched until etching reaches the intergate insulating film using the mask material as a mask to form a control gate electrode. Thereafter, the intergate insulating film is etched using the mask material and the control gate electrode as a mask under the condition of selectivity lower than the floating gate electrode material. However, if the intergate insulating film is etched under the foregoing condition, the floating gate electrode material is etched likewise. In other words, if the floating gate electrode is formed thicker to improve a coupling ratio, the intergate insulating film formed at the sidewall of the floating gate electrode is formed higher. For this reason, it is difficult to secure a process margin for fully removing the intergate insulating film on the sidewall of the floating gate electrode and for securing the thickness of the floating gate electrode.
Moreover, the following problem arises if the intergate insulating film remains on the sidewall of the floating gate electrode. When etching the floating gate electrode material using the mask material and the control gate electrode as a mask after that, the floating gate electrode material is not fully etched. For this reason, there is the following possibility. That is, floating gate electrodes neighboring in the direction perpendicular to an extended line of the control gate electrode mutually short-circuit.
In order to improve the selectivity of the floating gate electrode material and the intergate insulating film, a dedicated chamber for a high selectivity gas is required. In addition, etching stop by reactive products must be avoided; for this reason, high process control is required.
On the other hand, the following method is given as another method of increasing the contact area of the floating gate electrode and the intergate insulating film. According to the method, the sectional structure of the floating gate electrode is varied (e.g., JPN. PAT. APPLN. KOKAI Publication No. 09-186257 and No. 2003-31702). In FIG. 6 of the foregoing Publication No. 09-186257, there is disclosed a converse T-shaped floating gate electrode. However, according to the invention disclosed in Publication No. 09-186257, the height of the protrusion is adjusted to increase a coupling capacitance. Therefore, process control of the intergate insulating film is not taken into consideration. The foregoing Publication No. 2003-31702 discloses the following non-volatile semiconductor memory device. The non-volatile semiconductor memory device has a three-layer floating gate electrode comprising first to third floating gate electrodes to increase an overlapping area of control and floating gate electrodes. However, Publication No. 2003-31702 has no consideration relevant to process control of the intergate insulating film. Consequently, it is desirable to develop a non-volatile semiconductor memory device, which can prevent reduction of a coupling capacitance, and securely remove an intergate insulating film, and a method of manufacturing the same.